`define DIV_WIDTH 32

module divider(
	input 	clk,
  input 	[`DIV_WIDTH-1:0] 	dividend,
	input 	[`DIV_WIDTH-1:0] 	divisor,
	input 	start,
	output 	[`DIV_WIDTH-1:0] quotient,
	output 	[`DIV_WIDTH-1:0] remainder,
	output	ready
);

 parameter
  INITIAL	= 	5'b00001,
	COMPARE	=		5'b00010,
	SUB			=		5'b00100,
	R_SHIFT	=		5'b01000,
	DONE	=			5'b10000;
// Define Internal registers

 reg [4:0] state, next_state;
 reg diff;
 reg [`DIV_WIDTH-1:0] r1,r2;
 reg count;
always @ (posedge clk)
	begin
		 @(posedge start)
	  		state <= INITIAL;
	 
				state <= next_state;
	end
// Next state logic


always @ (state)
begin
 case (state)

INITIAL: begin
				next_state <= COMPARE;
					end

COMPARE: begin
				 if (diff)
				next_state <= SUB;
					else
				next_state <= R_SHIFT;
					end

SUB: 		begin
				next_state <= R_SHIFT;
				end

R_SHIFT: begin
				next_state <= DONE;
				 end

DONE:		begin
				next_state <= INITIAL;
				end

default:begin
				next_state <= INITIAL;
  			end
   endcase
end	
 
// Output genration logic
always @ (state)
begin
 case (state)

INITIAL: begin
				count <= 0;
				r2 <= divisor;
				
					end

COMPsARE: begin
				 if (diff)
				next_state <= SUB;
					else
				next_state <= R_SHIFT;
					end

SUB: 		begin
				next_state <= R_SHIFT;
				end

R_SHIFT: begin
				next_state <= DONE;
				 end

DONE:		begin
				next_state <= INITIAL;
				end

default:begin
				next_state <= INITIAL;
  			end
   endcase
end	
     
endmodule

    


